Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes

We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix are processed sequentially, or layer after layer. The maximum n...

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Bibliographic Details
Published in:2011 IEEE International Symposium of Circuits and Systems (ISCAS) pp. 1776 - 1779
Main Authors: Yang Sun, Guohui Wang, Cavallaro, J. R.
Format: Conference Proceeding
Language:English
Published: IEEE 01.05.2011
Subjects:
Decoding
IEEE 802.11n Standard
Parallel processing
Parity check codes
Registers
Throughput
Very large scale integration
ISBN:1424494737, 9781424494736
ISSN:0271-4302
Online Access:Get full text
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Summary:We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix are processed sequentially, or layer after layer. The maximum number of rows that can be simultaneously processed by the conventional layered decoder is limited to the sub-matrix size. To remove this limitation and support layer-level parallelism, we extend the conventional layered decoding algorithm and architecture to enable simultaneously processing of multiple (K) layers of a parity check matrix, which will lead to a roughly K-fold throughput increase. As a case study, we have designed a double-layer parallel LDPC decoder for the IEEE 802.11n standard. The decoder was synthesized for a TSMC 45-nm CMOS technology. With a synthesis area of 0.81 mm 2 and a maximum clock frequency of 815 MHz, the decoder achieves a maximum throughput of 3.0 Gbps at 15 iterations.
ISBN:1424494737
9781424494736
ISSN:0271-4302
DOI:10.1109/ISCAS.2011.5937928