Sun, Y., Wang, G., & Cavallaro, J. R. (2011, May). Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes. 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 1776-1779. https://doi.org/10.1109/ISCAS.2011.5937928
Chicago-Zitierstil (17. Ausg.)Sun, Yang, Guohui Wang, und J. R. Cavallaro. "Multi-layer Parallel Decoding Algorithm and Vlsi Architecture for Quasi-cyclic LDPC Codes." 2011 IEEE International Symposium of Circuits and Systems (ISCAS) May. 2011: 1776-1779. https://doi.org/10.1109/ISCAS.2011.5937928.
MLA-Zitierstil (9. Ausg.)Sun, Yang, et al. "Multi-layer Parallel Decoding Algorithm and Vlsi Architecture for Quasi-cyclic LDPC Codes." 2011 IEEE International Symposium of Circuits and Systems (ISCAS), May. 2011, pp. 1776-1779, https://doi.org/10.1109/ISCAS.2011.5937928.