Designing energy-efficient approximate adders using parallel genetic algorithms

Approximate computing involves selectively reducing the number of transistors in a circuit to improve energy savings. Energy savings may be achieved at the cost of reduced accuracy for signal processing applications whereby constituent adder and multiplier circuits need not generate a precise output...

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Vydané v:SoutheastCon 2015 s. 1 - 7
Hlavní autori: Naseer, Adnan Aquib, Ashraf, Rizwan A., Dechev, Damian, DeMara, Ronald F.
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 01.04.2015
Predmet:
adder
Adders
approximate computing
Approximation methods
delay
error distance
Genetic algorithms
inexact arithmetic units
low power
Mathematical model
Mirrors
parallel genetic algorithm
parallelism
power consumption
power reduction
process variation
Sociology
Statistics
variable accuracy
ISSN:1091-0050
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Abstract Approximate computing involves selectively reducing the number of transistors in a circuit to improve energy savings. Energy savings may be achieved at the cost of reduced accuracy for signal processing applications whereby constituent adder and multiplier circuits need not generate a precise output. Since the performance versus energy savings landscape is complex, we investigate the acceleration of the design of approximate adders using parallelized Genetic Algorithms (GAs). The fitness evaluation of each approximate adder is explored by the GA in a non-sequential fashion to automatically generate novel approximate designs within specified performance thresholds. This paper advances methods of parallelizing GAs and implements a new parallel GA approach for approximate multi-bit adder design. A speedup of approximately 1.6-fold is achieved using a quad-core Intel processor and results indicate that the proposed GA is able to find adders which consume 63:8% less energy than accurate adders.
AbstractList Approximate computing involves selectively reducing the number of transistors in a circuit to improve energy savings. Energy savings may be achieved at the cost of reduced accuracy for signal processing applications whereby constituent adder and multiplier circuits need not generate a precise output. Since the performance versus energy savings landscape is complex, we investigate the acceleration of the design of approximate adders using parallelized Genetic Algorithms (GAs). The fitness evaluation of each approximate adder is explored by the GA in a non-sequential fashion to automatically generate novel approximate designs within specified performance thresholds. This paper advances methods of parallelizing GAs and implements a new parallel GA approach for approximate multi-bit adder design. A speedup of approximately 1.6-fold is achieved using a quad-core Intel processor and results indicate that the proposed GA is able to find adders which consume 63:8% less energy than accurate adders.
Author DeMara, Ronald F.
Dechev, Damian
Ashraf, Rizwan A.
Naseer, Adnan Aquib
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  givenname: Adnan Aquib
  surname: Naseer
  fullname: Naseer, Adnan Aquib
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  givenname: Rizwan A.
  surname: Ashraf
  fullname: Ashraf, Rizwan A.
  organization: Dept. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA
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  givenname: Damian
  surname: Dechev
  fullname: Dechev, Damian
  organization: Dept. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA
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  givenname: Ronald F.
  surname: DeMara
  fullname: DeMara, Ronald F.
  email: demara@mail.ucf.edu
  organization: Dept. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA
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SubjectTerms adder
Adders
approximate computing
Approximation methods
delay
error distance
Genetic algorithms
inexact arithmetic units
low power
Mathematical model
Mirrors
parallel genetic algorithm
parallelism
power consumption
power reduction
process variation
Sociology
Statistics
variable accuracy
Title Designing energy-efficient approximate adders using parallel genetic algorithms
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