A fast bit loading algorithm synchronized with commercial power supply for in-home PLC systems - Honda, S.; Umehara, D.; Hayasaki, T.; Denno, S.; Morikura, M. (2008 IEEE International Symposium on Power Line Communications and Its Applications, 2008)
In-home PLC (power line communication) is one of the most attractive in-home networkings. However, there are a lot of technical issues for the realization of PLC with high rate and high reliability. These issues include the influence of frequency selective and linear periodically time-variant (LPTV) channel synchronized with commercial power supply. In particular, we show that some kind of switching power devices impact deep and deterministic time selectivity for power line channels. The combination of OFDM (Orthogonal Frequency Division Multiplexing) and bit loading algorithm is a powerful tool to increase the bit rate or reliability for quasi-static frequency selective channels including power line channels. However, a quick response will be required for the execution of bit loading algorithm since power line channels are synchronized with commercial power supply. In this paper, we propose a fast bit loading algorithm based on the fractional knapsack algorithm to enhance the bit rate under the condition that the transmitted power is constant. Furthermore, we evaluate the achievable bit rate of the proposed algorithm for the SNR over a power line channel and compare it with the achievable bit rate based on water filling theory.