Design methodologies and circuit optimization techniques for low power CMOS VLSI design - Geetha, B. T.; Padmavathi, B.; Perumal, V. (2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI), 2017)
Low power is the real test for late hardware businesses. Control scattering is an essential thought as far as execution and area for VLSI Chip outline. Control administration procedures are for the most part used to configuration low power circuits and frameworks. Insights demonstrate that 40% or considerably higher rate of the aggregate power utilization is because of the leakage of transistors. This rate will increment with innovation scaling unless streamlining methods are acquainted with bring leakage inside points of confinement. This paper concentrates on circuit improvement and plan mechanization strategies to fulfill this target. It additionally portrays many issues with respect to circuit outline at building, legitimate and gadget levels and exhibits different procedures to beat the previously mentioned issues. The initial segment of the paper gives a diagram of primary wellsprings of leakage current in CMOS transistor. The second part of the paper depicts various circuit streamlining procedures for controlling the standby leakage current. Some leakage current lessening procedures like rest approach; stack approach, and lector strategy are talked about for planning CMOS entryways which fundamentally chops down the leakage streams. The benefits of lector method are it doesn't require any extra control and observing hardware, in this way constraining the range increment and furthermore the power dissipation in dynamic state when contrasted with different systems and it doesn't influence the dynamic power which is the significant confinement with the other leakage diminishment strategies, is likewise examined in this paper.