Geetha, B. T., Padmavathi, B., & Perumal, V. (2017, September). Design methodologies and circuit optimization techniques for low power CMOS VLSI design. 2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI), 1759-1763. https://doi.org/10.1109/ICPCSI.2017.8392016
Chicago-Zitierstil (17. Ausg.)Geetha, B. T., B. Padmavathi, und V. Perumal. "Design Methodologies and Circuit Optimization Techniques for Low Power CMOS VLSI Design." 2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI) Sep. 2017: 1759-1763. https://doi.org/10.1109/ICPCSI.2017.8392016.
MLA-Zitierstil (9. Ausg.)Geetha, B. T., et al. "Design Methodologies and Circuit Optimization Techniques for Low Power CMOS VLSI Design." 2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI), Sep. 2017, pp. 1759-1763, https://doi.org/10.1109/ICPCSI.2017.8392016.