A self-testing and calibration technique for current-steering DACs

In this paper, a current-steering DAC self-testing and calibration technique is proposed. In the proposed scheme, the lower bits of the DAC are duplicated and an analog comparator is added to facilitate self-testing and calibration. In self- testing mode, the controller executes the self-testing alg...

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Bibliographic Details
Published in:2008 International Symposiium on VLSI Design, Automation and Test pp. 295 - 298
Main Authors: Yuan-Lang Ma, Jiun-Lang Huang
Format: Conference Proceeding
Language:English
Published: IEEE 01.04.2008
Subjects:
Built-in self-test
Calibration
Circuit testing
Decoding
Digital signal processing
Digital-analog conversion
Fuses
Prototypes
Signal processing algorithms
Voltage
ISBN:1424416167, 9781424416165
Online Access:Get full text
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Summary:In this paper, a current-steering DAC self-testing and calibration technique is proposed. In the proposed scheme, the lower bits of the DAC are duplicated and an analog comparator is added to facilitate self-testing and calibration. In self- testing mode, the controller executes the self-testing algorithm to characterize the DAC higher bits and computes the calibration information. In function mode, it produces the inputs to the duplicated lower bits for calibration. To validate the idea, a 14-bit prototype has been fabricated using TSMC 0.35 mum technology. The measurement results show that INL, DNL, and SFDR are significantly improved.
ISBN:1424416167
9781424416165
DOI:10.1109/VDAT.2008.4542471