New efficient hardware design methodology for modified non-restoring square root algorithm

This paper shows a new methodology to design the hardware for computing square root of N-bit unsigned numbers. The proposed hardware design is based on the modified non-restoring square root algorithm. Two different hardware designs, sequential pipeline architecture and asynchronous architecture for...

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Veröffentlicht in:	2014 International Conference on Informatics, Electronics and Vision (ICIEV) S. 1 - 6
Hauptverfasser:	Rahman, Atul, Abdullah-Al-Kafi
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 01.05.2014
Schlagworte:	Algorithm design and analysis clock cyle latency Clocks Computer architecture Field programmable gate arrays FPGA Hardware hardware resources maximum operating frequency modified non-restoring square root algorithm pipeline Pipelines Synchronization
ISBN:	147995179X, 9781479951796
Online-Zugang:	Volltext
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