APA (7th ed.) Citation

Sharma, S., Mukherjee, A., Dongre, A., & Sharad, M. (2017, January). Ultra Low Power Sensor Node for Security Applications, Facilitated by Algorithm-Architecture Co-design. VLSI design, 101-106. https://doi.org/10.1109/VLSID.2017.55

Chicago Style (17th ed.) Citation

Sharma, Saransh, Avilash Mukherjee, Abhishek Dongre, and Mrigank Sharad. "Ultra Low Power Sensor Node for Security Applications, Facilitated by Algorithm-Architecture Co-design." VLSI Design Jan. 2017: 101-106. https://doi.org/10.1109/VLSID.2017.55.

MLA (9th ed.) Citation

Sharma, Saransh, et al. "Ultra Low Power Sensor Node for Security Applications, Facilitated by Algorithm-Architecture Co-design." VLSI Design, Jan. 2017, pp. 101-106, https://doi.org/10.1109/VLSID.2017.55.