Hardware/Software co-design of a key point detector on FPGA

The design and implementing of a key point detector on embedded reconfigurable hardware is investigated. The major challenges are efficient hardware/software partitioning of the key point detector algorithm, data flow management as well as efficient use of memory, bus and processor. We present a mod...

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Bibliographic Details
Published in:FCCM 2007 : 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines : 23-25 April, 2007, Napa, California pp. 355 - 356
Main Authors: Chati, H.D., Muhlbauer, F., Braun, T., Bobda, C., Berns, K.
Format: Conference Proceeding
Language:English
Published: IEEE 01.04.2007
Subjects:
Change detection algorithms
Convolution
Detectors
Embedded computing
Embedded system
Field programmable gate arrays
Hardware
Object detection
Partitioning algorithms
Robots
ISBN:9780769529400, 0769529402
Online Access:Get full text
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Summary:The design and implementing of a key point detector on embedded reconfigurable hardware is investigated. The major challenges are efficient hardware/software partitioning of the key point detector algorithm, data flow management as well as efficient use of memory, bus and processor. We present a modular and manual hardware/software co-design, with its implementation on a Xilinx XUP-Virtex II Pro board co-design to solve these issues.
ISBN:9780769529400
0769529402
DOI:10.1109/FCCM.2007.61