Hardware/Software co-design of a key point detector on FPGA

The design and implementing of a key point detector on embedded reconfigurable hardware is investigated. The major challenges are efficient hardware/software partitioning of the key point detector algorithm, data flow management as well as efficient use of memory, bus and processor. We present a mod...

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Vydáno v:FCCM 2007 : 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines : 23-25 April, 2007, Napa, California s. 355 - 356
Hlavní autoři: Chati, H.D., Muhlbauer, F., Braun, T., Bobda, C., Berns, K.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.04.2007
Témata:
Change detection algorithms
Convolution
Detectors
Embedded computing
Embedded system
Field programmable gate arrays
Hardware
Object detection
Partitioning algorithms
Robots
ISBN:9780769529400, 0769529402
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Abstract The design and implementing of a key point detector on embedded reconfigurable hardware is investigated. The major challenges are efficient hardware/software partitioning of the key point detector algorithm, data flow management as well as efficient use of memory, bus and processor. We present a modular and manual hardware/software co-design, with its implementation on a Xilinx XUP-Virtex II Pro board co-design to solve these issues.
AbstractList The design and implementing of a key point detector on embedded reconfigurable hardware is investigated. The major challenges are efficient hardware/software partitioning of the key point detector algorithm, data flow management as well as efficient use of memory, bus and processor. We present a modular and manual hardware/software co-design, with its implementation on a Xilinx XUP-Virtex II Pro board co-design to solve these issues.
Author Braun, T.
Bobda, C.
Chati, H.D.
Berns, K.
Muhlbauer, F.
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  fullname: Berns, K.
  organization: Kaiserslautern Univ. of Technol., Kaiserslautern
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StartPage 355
SubjectTerms Change detection algorithms
Convolution
Detectors
Embedded computing
Embedded system
Field programmable gate arrays
Hardware
Object detection
Partitioning algorithms
Robots
Title Hardware/Software co-design of a key point detector on FPGA
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