Locally-clocked dynamic logic

Locally-clocked (LC) dynamic logic is a circuit methodology which combines a localized clocking strategy with a robust dynamic gate design to provide a high throughput, low latency circuit solution. LC dynamic logic creates event-driven pipelines which outperform and avoid many of the problems assoc...

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Veröffentlicht in:Circuits and Systems; Proceedings: Midwest Symposium on Circuits and Systems S. 18 - 21
Hauptverfasser: Hoyer, G., Gin Yee, Sechen, C.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 1998
Schlagworte:
Circuits
Clocks
CMOS technology
Delay effects
Frequency
Logic design
Logic devices
Pipelines
Space vector pulse width modulation
Throughput
ISBN:9780818689147, 0818689145
Online-Zugang:Volltext
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Beschreibung
Zusammenfassung:Locally-clocked (LC) dynamic logic is a circuit methodology which combines a localized clocking strategy with a robust dynamic gate design to provide a high throughput, low latency circuit solution. LC dynamic logic creates event-driven pipelines which outperform and avoid many of the problems associated with conventional clock-based pipeline techniques. LC dynamic logic was used to implement an 8/spl times/8 bit multiplier design that operates at 715 MHz in a 1.0 /spl mu/m MOSIS process, which exceeds the highest multiplier frequency previously published.
ISBN:9780818689147
0818689145
DOI:10.1109/MWSCAS.1998.759425