Locally-clocked dynamic logic - Hoyer, G.; Gin Yee; Sechen, C. (Circuits and Systems; Proceedings: Midwest Symposium on Circuits and Systems, 1998)
Locally-clocked (LC) dynamic logic is a circuit methodology which combines a localized clocking strategy with a robust dynamic gate design to provide a high throughput, low latency circuit solution. LC dynamic logic creates event-driven pipelines which outperform and avoid many of the problems associated with conventional clock-based pipeline techniques. LC dynamic logic was used to implement an 8/spl times/8 bit multiplier design that operates at 715 MHz in a 1.0 /spl mu/m MOSIS process, which exceeds the highest multiplier frequency previously published.