Locally-clocked dynamic logic
Locally-clocked (LC) dynamic logic is a circuit methodology which combines a localized clocking strategy with a robust dynamic gate design to provide a high throughput, low latency circuit solution. LC dynamic logic creates event-driven pipelines which outperform and avoid many of the problems assoc...
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| Vydáno v: | Circuits and Systems; Proceedings: Midwest Symposium on Circuits and Systems s. 18 - 21 |
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| Hlavní autoři: | , , |
| Médium: | Konferenční příspěvek |
| Jazyk: | angličtina |
| Vydáno: |
IEEE
1998
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| Témata: | |
| ISBN: | 9780818689147, 0818689145 |
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| Abstract | Locally-clocked (LC) dynamic logic is a circuit methodology which combines a localized clocking strategy with a robust dynamic gate design to provide a high throughput, low latency circuit solution. LC dynamic logic creates event-driven pipelines which outperform and avoid many of the problems associated with conventional clock-based pipeline techniques. LC dynamic logic was used to implement an 8/spl times/8 bit multiplier design that operates at 715 MHz in a 1.0 /spl mu/m MOSIS process, which exceeds the highest multiplier frequency previously published. |
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| AbstractList | Locally-clocked (LC) dynamic logic is a circuit methodology which combines a localized clocking strategy with a robust dynamic gate design to provide a high throughput, low latency circuit solution. LC dynamic logic creates event-driven pipelines which outperform and avoid many of the problems associated with conventional clock-based pipeline techniques. LC dynamic logic was used to implement an 8/spl times/8 bit multiplier design that operates at 715 MHz in a 1.0 /spl mu/m MOSIS process, which exceeds the highest multiplier frequency previously published. |
| Author | Gin Yee Sechen, C. Hoyer, G. |
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| DOI | 10.1109/MWSCAS.1998.759425 |
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| PublicationTitle | Circuits and Systems; Proceedings: Midwest Symposium on Circuits and Systems |
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| Snippet | Locally-clocked (LC) dynamic logic is a circuit methodology which combines a localized clocking strategy with a robust dynamic gate design to provide a high... |
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| SubjectTerms | Circuits Clocks CMOS technology Delay effects Frequency Logic design Logic devices Pipelines Space vector pulse width modulation Throughput |
| Title | Locally-clocked dynamic logic |
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