Some new algorithms for reconfiguring VLSI/WSI arrays

Deals with the issue of reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources. The models discussed consist of a set of identical Processing Elements (PEs) embedded in a flexible interconnection structure that is configured in the form of a rectangular grid...

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Veröffentlicht in:1990 proceedings S. 229 - 235
Hauptverfasser: Varvarigou, T., Roychowdhury, V.P., Kailath, T.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE Comput. Soc. Press 1990
Schlagworte:
Contracts
Fault tolerance
Hardware
Logic arrays
Management information systems
Reconfigurable architectures
Semiconductor device modeling
Switches
Very large scale integration
Wafer scale integration
ISBN:9780818690136, 0818690135
Online-Zugang:Volltext
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Beschreibung
Zusammenfassung:Deals with the issue of reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources. The models discussed consist of a set of identical Processing Elements (PEs) embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. Furthermore in order to incorporate fault tolerance a given array has a pre-determined distribution of spare PEs. The general issue in reconfiguration is to replace faulty non-spare PEs by healthy spare ones, subject to given hardware constraints. The authors present some new algorithms for reconfiguring N*(N+1) arrays (where the spare PEs are configured in the form of a spare row) into N*N arrays when N of the PEs are faulty. The algorithms developed are simple and perform better than other reconfiguration algorithms presented in the literature.< >
ISBN:9780818690136
0818690135
DOI:10.1109/ICWSI.1990.63905