Some new algorithms for reconfiguring VLSI/WSI arrays

Deals with the issue of reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources. The models discussed consist of a set of identical Processing Elements (PEs) embedded in a flexible interconnection structure that is configured in the form of a rectangular grid...

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Vydáno v:1990 proceedings s. 229 - 235
Hlavní autoři: Varvarigou, T., Roychowdhury, V.P., Kailath, T.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE Comput. Soc. Press 1990
Témata:
Contracts
Fault tolerance
Hardware
Logic arrays
Management information systems
Reconfigurable architectures
Semiconductor device modeling
Switches
Very large scale integration
Wafer scale integration
ISBN:9780818690136, 0818690135
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Abstract Deals with the issue of reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources. The models discussed consist of a set of identical Processing Elements (PEs) embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. Furthermore in order to incorporate fault tolerance a given array has a pre-determined distribution of spare PEs. The general issue in reconfiguration is to replace faulty non-spare PEs by healthy spare ones, subject to given hardware constraints. The authors present some new algorithms for reconfiguring N*(N+1) arrays (where the spare PEs are configured in the form of a spare row) into N*N arrays when N of the PEs are faulty. The algorithms developed are simple and perform better than other reconfiguration algorithms presented in the literature.< >
AbstractList Deals with the issue of reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources. The models discussed consist of a set of identical Processing Elements (PEs) embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. Furthermore in order to incorporate fault tolerance a given array has a pre-determined distribution of spare PEs. The general issue in reconfiguration is to replace faulty non-spare PEs by healthy spare ones, subject to given hardware constraints. The authors present some new algorithms for reconfiguring N*(N+1) arrays (where the spare PEs are configured in the form of a spare row) into N*N arrays when N of the PEs are faulty. The algorithms developed are simple and perform better than other reconfiguration algorithms presented in the literature.< >
Author Varvarigou, T.
Roychowdhury, V.P.
Kailath, T.
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  organization: Inf. Syst. Lab., Stanford Univ., CA, USA
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Snippet Deals with the issue of reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources. The models discussed consist of a set...
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StartPage 229
SubjectTerms Contracts
Fault tolerance
Hardware
Logic arrays
Management information systems
Reconfigurable architectures
Semiconductor device modeling
Switches
Very large scale integration
Wafer scale integration
Title Some new algorithms for reconfiguring VLSI/WSI arrays
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