A current-mode approach to CMOS neural network implementation - Watanabe, K.; Wang, L.; Cha, H.-W.; Ogawa, S. (1997 3rd International Conference on Algorithms and Architectures for Parallel Processing : ICA³PP/97 : Melbourne, Australia, December 10-12, 1997, 1997)
CMOS equivalents of the synapse and the neuron are proposed for LSI implementation of an adaptive analog neural network. The synapse is a multiplying digital-to-analog converter based on an R-2R ladder and the neuron consists of the second-generation current conveyor. Prototype chips fabricated independently using 0.6 /spl mu/m CMOS process have confirmed the wideband signal processing capability owing to a fully current-mode approach. Detailed analyses of measured performances have also given the design criteria for fully parallel implementation.