A global code scheduling technique using guarded PDG

For instruction-level parallel machines, it is essential to extract parallelly executable instructions from a program by code scheduling. In this paper, we propose a new code scheduling technique using an extension of PDG. This technique parallelizes non-numerical programs, producing better machine...

Full description

Bibliographic Details

Published in:	IEEE First ICA³PP, IEEE First International Conference on Algorithms and Architectures for Parallel Processing, Brisbane, Australia, 19-21 April, 1995 Vol. 2; pp. 661 - 669 vol.2
Main Authors:	Koseki, A., Komatsu, H., Fukazawa, Y.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.01.1995
Subjects:	Arithmetic Computer aided instruction Concurrent computing Dynamic scheduling Laboratories Processor scheduling
ISBN:	9780780320185, 0780320182
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!