Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware

TCP/IP is the predominant communication protocol in modern networks but also one of the most demanding. Consequently, TCP/IP offload is becoming increasingly popular with standard network interface cards. TCP/IP Offload Engines have also emerged for FPGAs, and are being offered by vendors such as In...

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Vydáno v:2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines s. 36 - 43
Hlavní autoři: Sidler, David, Alonso, Gustavo, Blott, Michaela, Karras, Kimon, Vissers, Kees, Carley, Raymond
Médium: Konferenční příspěvek
Jazyk:angličtina
japonština
Vydáno: IEEE 01.05.2015
Témata:
10G network stack
Data structures
Engines
Field programmable gate arrays
High session count
High-level Synthesis (HLS)
IP networks
Ports (Computers)
Protocols
Reconfigurable Hardware
TCP/IP
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Shrnutí:TCP/IP is the predominant communication protocol in modern networks but also one of the most demanding. Consequently, TCP/IP offload is becoming increasingly popular with standard network interface cards. TCP/IP Offload Engines have also emerged for FPGAs, and are being offered by vendors such as Intilop, Fraunhofer HHI, PLDA and Dini Group. With the target application being high-frequency trading, these implementations focus on low latency and support a limited session count. However, many more applications beyond high-frequency trading can potentially be accelerated inside an FPGA once TCP with high session count is available inside the fabric. This way, a network-attached FPGA on ingress and egress to a CPU can accelerate functions such as encryption, compression, memcached and many others in addition to running the complete network stack. This paper introduces a novel architecture for a 10Gbps line-rate TCP/IP stack for FPGAs that can scale with the number of sessions and thereby addresses these new applications. We prototyped the design on a VC709 development board, demonstrating compatibility with existing network infrastructure, operating at full 10Gbps throughput full-duplex while supporting 10,000 sessions. Finally, the design has been described primarily using high-level synthesis, which accelerates development time and improves maintainability.
DOI:10.1109/FCCM.2015.12