Initial study of a phase-aware scheduling for hardware transactional memory

Transactional memory is a promising paradigm for shared memory parallel programming model. Effective transaction scheduling is very important for transactional memory systems, and a substantial body of work has been conducted. We have proposed a transaction scheduling which considers execution path...

Full description

Saved in:

Bibliographic Details
Published in:	2017 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM) pp. 1 - 6
Main Authors:	Tajimi, Tomoki, Hirota, Anju, Shioya, Ryota, Goshima, Masahiro, Tsumura, Tomoaki
Format:	Conference Proceeding
Language:	English Japanese
Published:	IEEE 01.08.2017
Subjects:	Benchmark testing History Measurement uncertainty Prediction algorithms Processor scheduling Program processors Scheduling
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Description
Summary:	Transactional memory is a promising paradigm for shared memory parallel programming model. Effective transaction scheduling is very important for transactional memory systems, and a substantial body of work has been conducted. We have proposed a transaction scheduling which considers execution path variation in transactions, and it goes well with many types of programs, but some programs still can not gain performance. In this paper, we focus on such programs and investigate the reason for low performance by analyzing conflict prediction accuracy and typical conflict patterns. Then, we propose a novel phase-aware transaction scheduling for resolving one of the harmful conflict patterns. Evaluation result shows that the phase-aware scheduling can largely improve the performance of one of the benchmark programs, and indicates its potential superiority.
DOI:	10.1109/PACRIM.2017.8121912