A superparallel image filtering digital-pixel-sensor employing a compressive multiplication technique

A full-pixel parallel image filtering architecture is developed based on the digital-pixel-sensor. A compressive multiplication technique is employed to accelerate the processing speed. As a result, speed-ups from 3.2 to 5.2 were achieved for Gaussian kernels ranged from 5×5 to 15×15 in scale-invari...

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Veröffentlicht in:	2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) S. 363 - 366
Hauptverfasser:	Hongbo Zhu, Asada, Kunihiro
Format:	Tagungsbericht
Sprache:	Englisch Japanisch
Veröffentlicht:	IEEE 01.12.2014
Schlagworte:	Computer architecture Feature extraction Image coding Image resolution Kernel Parallel processing Random access memory
Online-Zugang:	Volltext
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