A superparallel image filtering digital-pixel-sensor employing a compressive multiplication technique
A full-pixel parallel image filtering architecture is developed based on the digital-pixel-sensor. A compressive multiplication technique is employed to accelerate the processing speed. As a result, speed-ups from 3.2 to 5.2 were achieved for Gaussian kernels ranged from 5×5 to 15×15 in scale-invari...
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| Vydáno v: | 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) s. 363 - 366 |
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| Jazyk: | angličtina japonština |
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IEEE
01.12.2014
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| Abstract | A full-pixel parallel image filtering architecture is developed based on the digital-pixel-sensor. A compressive multiplication technique is employed to accelerate the processing speed. As a result, speed-ups from 3.2 to 5.2 were achieved for Gaussian kernels ranged from 5×5 to 15×15 in scale-invariant feature transform (SIFT) algorithm. A 108 × 96-pixel sensor was designed using a 0.18 μm CMOS process in a 5 mm×5 mm chip. By simulating the sensor at 100 MHz, the image filtering times for 5×5, 7×7, and 9×9 Gaussian kernels in the SIFT algorithm are 34 μs, 49 μs, and 83 μs, respectively. Such a high processing speed is very important for achieving the real-time performance when filtering high resolution images with large kernels. |
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| AbstractList | A full-pixel parallel image filtering architecture is developed based on the digital-pixel-sensor. A compressive multiplication technique is employed to accelerate the processing speed. As a result, speed-ups from 3.2 to 5.2 were achieved for Gaussian kernels ranged from 5×5 to 15×15 in scale-invariant feature transform (SIFT) algorithm. A 108 × 96-pixel sensor was designed using a 0.18 μm CMOS process in a 5 mm×5 mm chip. By simulating the sensor at 100 MHz, the image filtering times for 5×5, 7×7, and 9×9 Gaussian kernels in the SIFT algorithm are 34 μs, 49 μs, and 83 μs, respectively. Such a high processing speed is very important for achieving the real-time performance when filtering high resolution images with large kernels. |
| Author | Asada, Kunihiro Hongbo Zhu |
| Author_xml | – sequence: 1 surname: Hongbo Zhu fullname: Hongbo Zhu email: zhu@vdec.u-tokyo.ac.jp organization: VLSI Design & Educ. Center (VDEC), Univ. of Tokyo, Tokyo, Japan – sequence: 2 givenname: Kunihiro surname: Asada fullname: Asada, Kunihiro email: asada@silicon.u-tokyo.ac.jp organization: VLSI Design & Educ. Center (VDEC), Univ. of Tokyo, Tokyo, Japan |
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| Snippet | A full-pixel parallel image filtering architecture is developed based on the digital-pixel-sensor. A compressive multiplication technique is employed to... |
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| SubjectTerms | Computer architecture Feature extraction Image coding Image resolution Kernel Parallel processing Random access memory |
| Title | A superparallel image filtering digital-pixel-sensor employing a compressive multiplication technique |
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