Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM

Vector accelerators can efficiently execute regular data-parallel workloads, but they require expensive multi-ported register files to feed large vector ALUs. Recent work on in-situ processing-in-SRAM shows promise in enabling area-efficient vector acceleration. This work explores two different appr...

Full description

Bibliographic Details

Published in:	IEEE International Symposium on Circuits and Systems proceedings pp. 1 - 5
Main Authors:	Al-Hawaj, Khalid, Afuye, Olalekan, Agwa, Shady, Apsel, Alyssa, Batten, Christopher
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.10.2020
Subjects:	Decoding Latches Layout Multiplexing Random access memory Registers Throughput
ISBN:	9781728133201, 1728133203
ISSN:	2158-1525
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!