Industry Paper: Surrogate Models for Testing Analog Designs under Limited Budget - a Bandgap Case Study

Testing analog integrated circuit (IC) designs is notoriously hard. Simulating tens of milliseconds from an accurate transistor level model of a complex analog design can take up to two weeks of computation. Therefore, the number of tests that can be executed during the late development stage of an...

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Vydané v:	International Conference on Hardware/Software Codesign and System Synthesis (Online) s. 21 - 24
Hlavní autori:	Bloem, Roderick, Larrauri, Alberto, Lengfeldner, Roland, Mateis, Cristinel, Nickovic, Dejan, Ziegler, Bjorn
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 01.10.2022
Predmet:	analog design Artificial neural networks Bayes methods Computational modeling Integrated circuit modeling machine learning Photonic band gap surrogate model testing Transistors Voltage
ISSN:	2832-6474
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