Industry Paper: Surrogate Models for Testing Analog Designs under Limited Budget - a Bandgap Case Study
Testing analog integrated circuit (IC) designs is notoriously hard. Simulating tens of milliseconds from an accurate transistor level model of a complex analog design can take up to two weeks of computation. Therefore, the number of tests that can be executed during the late development stage of an...
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| Vydáno v: | International Conference on Hardware/Software Codesign and System Synthesis (Online) s. 21 - 24 |
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| Hlavní autoři: | , , , , , |
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| Jazyk: | angličtina |
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IEEE
01.10.2022
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| ISSN: | 2832-6474 |
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| Abstract | Testing analog integrated circuit (IC) designs is notoriously hard. Simulating tens of milliseconds from an accurate transistor level model of a complex analog design can take up to two weeks of computation. Therefore, the number of tests that can be executed during the late development stage of an analog IC can be very limited. We leverage the recent advancements in machine learning (ML) and propose two techniques, artificial neural networks (ANN) and Gaussian processes, to learn a surrogate model from an existing test suite. We then explore the surrogate model with Bayesian optimization to guide the generation of additional tests. We use an industrial bandgap case study to evaluate the two approaches and demonstrate the virtue of Bayesian optimization in efficiently generating complementary tests with constrained effort. |
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| AbstractList | Testing analog integrated circuit (IC) designs is notoriously hard. Simulating tens of milliseconds from an accurate transistor level model of a complex analog design can take up to two weeks of computation. Therefore, the number of tests that can be executed during the late development stage of an analog IC can be very limited. We leverage the recent advancements in machine learning (ML) and propose two techniques, artificial neural networks (ANN) and Gaussian processes, to learn a surrogate model from an existing test suite. We then explore the surrogate model with Bayesian optimization to guide the generation of additional tests. We use an industrial bandgap case study to evaluate the two approaches and demonstrate the virtue of Bayesian optimization in efficiently generating complementary tests with constrained effort. |
| Author | Mateis, Cristinel Ziegler, Bjorn Nickovic, Dejan Bloem, Roderick Larrauri, Alberto Lengfeldner, Roland |
| Author_xml | – sequence: 1 givenname: Roderick surname: Bloem fullname: Bloem, Roderick organization: Graz University of Technology,Austria – sequence: 2 givenname: Alberto surname: Larrauri fullname: Larrauri, Alberto organization: Graz University of Technology,Austria – sequence: 3 givenname: Roland surname: Lengfeldner fullname: Lengfeldner, Roland organization: Graz University of Technology,Austria – sequence: 4 givenname: Cristinel surname: Mateis fullname: Mateis, Cristinel organization: Graz University of Technology,Austria – sequence: 5 givenname: Dejan surname: Nickovic fullname: Nickovic, Dejan organization: Graz University of Technology,Austria – sequence: 6 givenname: Bjorn surname: Ziegler fullname: Ziegler, Bjorn organization: Graz University of Technology,Austria |
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| Snippet | Testing analog integrated circuit (IC) designs is notoriously hard. Simulating tens of milliseconds from an accurate transistor level model of a complex analog... |
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| StartPage | 21 |
| SubjectTerms | analog design Artificial neural networks Bayes methods Computational modeling Integrated circuit modeling machine learning Photonic band gap surrogate model testing Transistors Voltage |
| Title | Industry Paper: Surrogate Models for Testing Analog Designs under Limited Budget - a Bandgap Case Study |
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