Scalable processor core for high-speed pattern matching architecture on FPGA

In recent pattern matching architecture researches, there has been much attention to high-throughput implementations with reconfiguration on the fly on FPGAs as well as ASICs. In this paper, we propose to use self-organizing approach to synthesize two-dimensional map (cluster) of a simple processing...

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Veröffentlicht in:	2016 Third International Conference on Digital Information Processing, Data Mining, and Wireless Communications (DIPDMWC) S. 148 - 153
Hauptverfasser:	Alyushin, A. V., Alyushin, S. A., Arkhangelsky, V. G.
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 01.07.2016
Schlagworte:	Bandwidth bit-vector Computer architecture Delay effects Field programmable gate arrays Field-Programmable Gate Array (FPGA) packet classification parallel architectures Pattern matching Random access memory self-organizing maps (SOM) stream pattern matching Switches
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