Scalable processor core for high-speed pattern matching architecture on FPGA
In recent pattern matching architecture researches, there has been much attention to high-throughput implementations with reconfiguration on the fly on FPGAs as well as ASICs. In this paper, we propose to use self-organizing approach to synthesize two-dimensional map (cluster) of a simple processing...
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| Veröffentlicht in: | 2016 Third International Conference on Digital Information Processing, Data Mining, and Wireless Communications (DIPDMWC) S. 148 - 153 |
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01.07.2016
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| Abstract | In recent pattern matching architecture researches, there has been much attention to high-throughput implementations with reconfiguration on the fly on FPGAs as well as ASICs. In this paper, we propose to use self-organizing approach to synthesize two-dimensional map (cluster) of a simple processing units with lateral links for fast pattern matching of one-dimensional input event. We suggest scalable processor core with heterogeneous cluster architecture. Experimental results show that the proposed architecture has advantages over the previously developed architectures in the terms of operating frequency, time delay and data bandwidth. For state-of-the-art FPGA we achieve operating frequency 600-500 MHz for the processor core with single cluster (input pattern of 8-512 bits, rule set of 64 bits), 490-440 MHz for the processor core with multiple clusters (rule set of 128 - 4096 bits, input pattern of 512 bits). Each cluster is characterized by low pipeline time delay of 3 ~ 5 clock cycles. |
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| AbstractList | In recent pattern matching architecture researches, there has been much attention to high-throughput implementations with reconfiguration on the fly on FPGAs as well as ASICs. In this paper, we propose to use self-organizing approach to synthesize two-dimensional map (cluster) of a simple processing units with lateral links for fast pattern matching of one-dimensional input event. We suggest scalable processor core with heterogeneous cluster architecture. Experimental results show that the proposed architecture has advantages over the previously developed architectures in the terms of operating frequency, time delay and data bandwidth. For state-of-the-art FPGA we achieve operating frequency 600-500 MHz for the processor core with single cluster (input pattern of 8-512 bits, rule set of 64 bits), 490-440 MHz for the processor core with multiple clusters (rule set of 128 - 4096 bits, input pattern of 512 bits). Each cluster is characterized by low pipeline time delay of 3 ~ 5 clock cycles. |
| Author | Arkhangelsky, V. G. Alyushin, S. A. Alyushin, A. V. |
| Author_xml | – sequence: 1 givenname: A. V. surname: Alyushin fullname: Alyushin, A. V. email: avalyushin@mail.ru organization: Moscow Eng. Phys. Inst., Nat. Res. Nucl. Univ. MEPHi, Moscow, Russia – sequence: 2 givenname: S. A. surname: Alyushin fullname: Alyushin, S. A. organization: Moscow Eng. Phys. Inst., Nat. Res. Nucl. Univ. MEPHi, Moscow, Russia – sequence: 3 givenname: V. G. surname: Arkhangelsky fullname: Arkhangelsky, V. G. email: citis@arkhang.ru organization: Centre of Inf. Technol. & Syst. for Executive Power Authorities, Moscow, Russia |
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| SubjectTerms | Bandwidth bit-vector Computer architecture Delay effects Field programmable gate arrays Field-Programmable Gate Array (FPGA) packet classification parallel architectures Pattern matching Random access memory self-organizing maps (SOM) stream pattern matching Switches |
| Title | Scalable processor core for high-speed pattern matching architecture on FPGA |
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