Alyushin, A. V., Alyushin, S. A., & Arkhangelsky, V. G. (2016, July). Scalable processor core for high-speed pattern matching architecture on FPGA. 2016 Third International Conference on Digital Information Processing, Data Mining, and Wireless Communications (DIPDMWC), 148-153. https://doi.org/10.1109/DIPDMWC.2016.7529380
Citace podle Chicago (17th ed.)Alyushin, A. V., S. A. Alyushin, a V. G. Arkhangelsky. "Scalable Processor Core for High-speed Pattern Matching Architecture on FPGA." 2016 Third International Conference on Digital Information Processing, Data Mining, and Wireless Communications (DIPDMWC) Jul. 2016: 148-153. https://doi.org/10.1109/DIPDMWC.2016.7529380.
Citace podle MLA (9th ed.)Alyushin, A. V., et al. "Scalable Processor Core for High-speed Pattern Matching Architecture on FPGA." 2016 Third International Conference on Digital Information Processing, Data Mining, and Wireless Communications (DIPDMWC), Jul. 2016, pp. 148-153, https://doi.org/10.1109/DIPDMWC.2016.7529380.