Low complexity modified constant Log-Map algorithm for radix-4 turbo decoder

Turbo decoding for 3GPP-LTE wireless communication standard is most challenging task to reduce computational complexity. This paper presents 8-state trellis VHDL implementation of radix-2 and radix-4 form. In a practical system, the original MAP algorithm is too complex for implementation. All the b...

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Vydáno v:2015 International Conference on Pervasive Computing (ICPC) s. 1 - 4
Hlavní autoři: Bahirgonde, Prabhavati D., Dixit, Shantanu K.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.01.2015
Témata:
3GPP-LTE
Approximation algorithms
Approximation methods
Decoding
FPGA
Hardware
LLR
MAX
Measurement
SISO
Table lookup
Turbo codes
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Abstract Turbo decoding for 3GPP-LTE wireless communication standard is most challenging task to reduce computational complexity. This paper presents 8-state trellis VHDL implementation of radix-2 and radix-4 form. In a practical system, the original MAP algorithm is too complex for implementation. All the branch metrics required for calculating LLR values are stored in a RAM. Max* function is implemented with correction factor to improve performance. The proposed, implemented algorithm is almost identical to max* function. With increasing demand for different data rate and services for communication system reconfigurability is important. So implementation is targeted towards Xilinx Virtex E FPGAs. The turbo decoder uses soft in soft out (SISO) decoders to decode one code word.
AbstractList Turbo decoding for 3GPP-LTE wireless communication standard is most challenging task to reduce computational complexity. This paper presents 8-state trellis VHDL implementation of radix-2 and radix-4 form. In a practical system, the original MAP algorithm is too complex for implementation. All the branch metrics required for calculating LLR values are stored in a RAM. Max* function is implemented with correction factor to improve performance. The proposed, implemented algorithm is almost identical to max* function. With increasing demand for different data rate and services for communication system reconfigurability is important. So implementation is targeted towards Xilinx Virtex E FPGAs. The turbo decoder uses soft in soft out (SISO) decoders to decode one code word.
Author Bahirgonde, Prabhavati D.
Dixit, Shantanu K.
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  givenname: Prabhavati D.
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  fullname: Bahirgonde, Prabhavati D.
  email: pshirwal@rediffmail.com
  organization: Dept. of Electron. & Telecommun. Eng., Walchand Inst. of Technol., Solapur, India
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  givenname: Shantanu K.
  surname: Dixit
  fullname: Dixit, Shantanu K.
  email: dixitshantanu1@gmail.com
  organization: Dept. of Electron. & Telecommun. Eng., Walchand Inst. of Technol., Solapur, India
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Snippet Turbo decoding for 3GPP-LTE wireless communication standard is most challenging task to reduce computational complexity. This paper presents 8-state trellis...
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SubjectTerms 3GPP-LTE
Approximation algorithms
Approximation methods
Decoding
FPGA
Hardware
LLR
MAX
Measurement
SISO
Table lookup
Turbo codes
Title Low complexity modified constant Log-Map algorithm for radix-4 turbo decoder
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