FPGA implementation for a recursive least square algorithm

A recursive least square algorithm is implemented in this paper. Memory Nonlinearity of digital receiver is compensated by using a blind identification algorithm based on nonlinear model. A least-squared blind identification criterion to minimize all the energy of the nonlinearity in the receiver�...

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Vydáno v:2013 2nd International Symposium on Instrumentation and Measurement, Sensor Network and Automation (IMSNA) s. 741 - 744
Hlavní autoři: Peng Liang, Sun Guocang, Deng Haihua, Chen Ming
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.12.2013
Témata:
Algorithm design and analysis
Calibration
Field programmable gate arrays
FPGA
Kernel
Matrix decomposition
matrix inversion
Nonlinear distortion
Receivers
recursive least square (RLS)
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Shrnutí:A recursive least square algorithm is implemented in this paper. Memory Nonlinearity of digital receiver is compensated by using a blind identification algorithm based on nonlinear model. A least-squared blind identification criterion to minimize all the energy of the nonlinearity in the receiver's output signal is implemented under circumstances of not knowing the information of the receiver's input signal. The orders and memory depths of the Volterra model are tested and updated automatically. A double-precision arbitrary-dimensional matrix inversion module is implemented in the requirement of the least-squared method. The digital post calibration processes in real-time. Experimental results on the actual nonlinear circuit illustrate the validity of the implemented technique.
DOI:10.1109/IMSNA.2013.6743383