Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation

Recently, there has been a sharp rise in demand for hardware implementations because of the improved accuracy of Convolutional Neural Networks (CNN) on a wide range of classification and recognition applications. To achieve the needed performance, they include heavy processor operations and memory b...

Celý popis

Podrobná bibliografia

Vydané v:	2023 4th IEEE Global Conference for Advancement in Technology (GCAT) s. 1 - 6
Hlavní autori:	Pandey, Jyoti, Asati, Abhijit R., Shenoy, Meetha V., Sikka, Prateek
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 06.10.2023
Predmet:	CNN Convolutional neural networks Deep learning Estimation Hardware Hardware design languages Hardware resource utilization High-level synthesis Logic gates MATLAB HDL coder Resource management Systems architecture
On-line prístup:	Získať plný text
Tagy:	Pridať tag Žiadne tagy, Buďte prvý, kto otaguje tento záznam!