Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation - Pandey, Jyoti; Asati, Abhijit R.; Shenoy, Meetha V.; Sikka, Prateek (2023 4th IEEE Global Conference for Advancement in Technology (GCAT), 2023)
Recently, there has been a sharp rise in demand for hardware implementations because of the improved accuracy of Convolutional Neural Networks (CNN) on a wide range of classification and recognition applications. To achieve the needed performance, they include heavy processor operations and memory bandwidth. For optimized hardware deployment, which necessitates thorough optimization of system architectures and algorithms to get particularly efficient designs, a target system's hardware resources and an estimation of its performance at a greater degree of abstraction are crucial. Since the programmable hardware fabric may be customized for each unique network, Field Programmable Gate Arrays (FPGA) can accomplish this efficiency in this situation. This paper shows the high-level synthesis (HLS) of each of the different layers of optimized CNN using the MATLAB HDL coder. Along with its HDL resource utilization report, we also investigated the computational processes and hardware resource estimation of the previously developed optimized CNN. The hardware resources required by all the convolutional and fully connected layers of the optimized CNN matches exactly will the previously calculated resources. So, the hardware resource utilization is verified through HLS. The architecture takes fixed-point math into account. All layers are synthesized in Vivado 2022.2 with the Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit as the target.