Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation
Recently, there has been a sharp rise in demand for hardware implementations because of the improved accuracy of Convolutional Neural Networks (CNN) on a wide range of classification and recognition applications. To achieve the needed performance, they include heavy processor operations and memory b...
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| Vydáno v: | 2023 4th IEEE Global Conference for Advancement in Technology (GCAT) s. 1 - 6 |
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IEEE
06.10.2023
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| Abstract | Recently, there has been a sharp rise in demand for hardware implementations because of the improved accuracy of Convolutional Neural Networks (CNN) on a wide range of classification and recognition applications. To achieve the needed performance, they include heavy processor operations and memory bandwidth. For optimized hardware deployment, which necessitates thorough optimization of system architectures and algorithms to get particularly efficient designs, a target system's hardware resources and an estimation of its performance at a greater degree of abstraction are crucial. Since the programmable hardware fabric may be customized for each unique network, Field Programmable Gate Arrays (FPGA) can accomplish this efficiency in this situation. This paper shows the high-level synthesis (HLS) of each of the different layers of optimized CNN using the MATLAB HDL coder. Along with its HDL resource utilization report, we also investigated the computational processes and hardware resource estimation of the previously developed optimized CNN. The hardware resources required by all the convolutional and fully connected layers of the optimized CNN matches exactly will the previously calculated resources. So, the hardware resource utilization is verified through HLS. The architecture takes fixed-point math into account. All layers are synthesized in Vivado 2022.2 with the Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit as the target. |
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| AbstractList | Recently, there has been a sharp rise in demand for hardware implementations because of the improved accuracy of Convolutional Neural Networks (CNN) on a wide range of classification and recognition applications. To achieve the needed performance, they include heavy processor operations and memory bandwidth. For optimized hardware deployment, which necessitates thorough optimization of system architectures and algorithms to get particularly efficient designs, a target system's hardware resources and an estimation of its performance at a greater degree of abstraction are crucial. Since the programmable hardware fabric may be customized for each unique network, Field Programmable Gate Arrays (FPGA) can accomplish this efficiency in this situation. This paper shows the high-level synthesis (HLS) of each of the different layers of optimized CNN using the MATLAB HDL coder. Along with its HDL resource utilization report, we also investigated the computational processes and hardware resource estimation of the previously developed optimized CNN. The hardware resources required by all the convolutional and fully connected layers of the optimized CNN matches exactly will the previously calculated resources. So, the hardware resource utilization is verified through HLS. The architecture takes fixed-point math into account. All layers are synthesized in Vivado 2022.2 with the Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit as the target. |
| Author | Pandey, Jyoti Shenoy, Meetha V. Sikka, Prateek Asati, Abhijit R. |
| Author_xml | – sequence: 1 givenname: Jyoti surname: Pandey fullname: Pandey, Jyoti email: p20180412@pilani.bits-pilani.ac.in organization: Birla Institute of Technology and Science (BITS-Pilani Campus),EEE Department,Pilani,Rajasthan,India – sequence: 2 givenname: Abhijit R. surname: Asati fullname: Asati, Abhijit R. email: abhijit_asati@pilani.bits-pilani.ac.in organization: Birla Institute of Technology and Science (BITS-Pilani Campus),EEE Department,Pilani,Rajasthan,India – sequence: 3 givenname: Meetha V. surname: Shenoy fullname: Shenoy, Meetha V. email: meetha.shenoy@pilani.bits-pilani.ac.in organization: Birla Institute of Technology and Science (BITS-Pilani Campus),EEE Department,Pilani,Rajasthan,India – sequence: 4 givenname: Prateek surname: Sikka fullname: Sikka, Prateek email: prateeksikka@gmail.com organization: STMicroelectronics,India |
| BookMark | eNo1j8tKw0AYhUfQhda-geC8QOJcMkn-ZQg2KQQUbd2WyfQfM5BLmaRKffoGq5tzFucC3x257oceCXnkLOScwVORZxsFkLBQMCFDzqSSkosrsoQEUqmYZEpwdkvqD_TOOqMnN_R0sLTUfv-tPdI3HIejN0i3k2vdz6UwNX44fja0dLNU-IUtfT_1U4OjG6kdPF29Fhldd4cWO-yn39E9ubG6HXH55wuyXT1v8jKoXop1nlWB4xymQMWordzXIkmjVEMkRWoMMh2lFpDHyhiGMragUjTcxIgQRyDqmQPmDIxckIfLr0PE3cG7TvvT7h9dngHB-VTe |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IL CBEJK RIE RIL |
| DOI | 10.1109/GCAT59970.2023.10353312 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Xplore POP ALL IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP All) 1998-Present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| EISBN | 9798350305210 9798350305258 |
| EndPage | 6 |
| ExternalDocumentID | 10353312 |
| Genre | orig-research |
| GroupedDBID | 6IE 6IL CBEJK RIE RIL |
| ID | FETCH-LOGICAL-i119t-56eaf3db27848a94328cce0a48f9e165cc0e36f958ec1c6ee96492b05295cc9c3 |
| IEDL.DBID | RIE |
| IngestDate | Wed Jan 10 09:27:52 EST 2024 |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-i119t-56eaf3db27848a94328cce0a48f9e165cc0e36f958ec1c6ee96492b05295cc9c3 |
| PageCount | 6 |
| ParticipantIDs | ieee_primary_10353312 |
| PublicationCentury | 2000 |
| PublicationDate | 2023-Oct.-6 |
| PublicationDateYYYYMMDD | 2023-10-06 |
| PublicationDate_xml | – month: 10 year: 2023 text: 2023-Oct.-6 day: 06 |
| PublicationDecade | 2020 |
| PublicationTitle | 2023 4th IEEE Global Conference for Advancement in Technology (GCAT) |
| PublicationTitleAbbrev | GCAT |
| PublicationYear | 2023 |
| Publisher | IEEE |
| Publisher_xml | – name: IEEE |
| Score | 1.8466644 |
| Snippet | Recently, there has been a sharp rise in demand for hardware implementations because of the improved accuracy of Convolutional Neural Networks (CNN) on a wide... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 1 |
| SubjectTerms | CNN Convolutional neural networks Deep learning Estimation Hardware Hardware design languages Hardware resource utilization High-level synthesis Logic gates MATLAB HDL coder Resource management Systems architecture |
| Title | Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation |
| URI | https://ieeexplore.ieee.org/document/10353312 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LSwMxEA4qHjypWPFNDl63bjaPTY6l2HqQUrCV3kqSncCCbqXdKv57kzRVPHjwFkIgMJPHZOb78iF0K0paOMt1xipR-QeKX8aSKZb5A1OAFIwYW0WxiXI0krOZGieyeuTCAEAEn0E3NGMtv1rYdUiV-R1OfXQSNIV3y1JsyFoJs0VydTfs9yZcqTLvBk3w7nb0L92UeG0MDv854RHq_BDw8Pj7ajlGO9CcIPPsV4tLOTa8cDhU3T_0EvA2B4-nbf2SiJU4KfDggOTAjwEbhJ8-Gx_vreoV9qEqHoyHPRx_B35NBKSmg6aD-0n_IUsSCVlNiGozLkA7WplQPpRaMVpIayHXTDoFRHBrc6DCKS7BEisAlGCqMLG8Z62y9BTtNYsGzhAuOKhcGEqMcYxWQmoOzMdv2qjSWCLPUScYaP62-QVjvrXNxR_9l-gguCEC38QV2muXa7hG-_a9rVfLm-i7L2WfnMo |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LSwMxEA5SBT2pWPFtDl63bjaPTY6l2FaspWArvZVNdgILupV2q_jvTdKt4sGDtxACgZk8JjPflw-hG5HSxBqeRSwXuXuguGUsmWKROzAFSMGINnkQm0iHQzmdqlFNVg9cGAAI4DNo-Wao5edzs_KpMrfDqYtOvKbwNmcsidd0rRq1RWJ12-u0x1ypNG55VfDWZvwv5ZRwcXT3_znlAWr-UPDw6PtyOURbUB4h_ezWi62zbHhusa-7f2QLwJssPJ5UxUtNrcS1Bg_2WA488Ogg_PRZuohvWSyxC1Zxd9Rr4_A_8GtNQSqbaNK9G3f6US2SEBWEqCriAjJLc-0LiDJTjCbSGIgzJq0CIrgxMVBhFZdgiBEASjCV6FDgM0YZeowa5byEE4QTDioWmhKtLaO5kBkH5iK4TKtUGyJPUdMbaPa2_gdjtrHN2R_912i3P34czAb3w4dztOddEmBw4gI1qsUKLtGOea-K5eIq-PELuk-gEQ |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2023+4th+IEEE+Global+Conference+for+Advancement+in+Technology+%28GCAT%29&rft.atitle=Verification+of+Hardware+Resource+Utilization+through+High+Level+Synthesis+for+FPGA+Implementation&rft.au=Pandey%2C+Jyoti&rft.au=Asati%2C+Abhijit+R.&rft.au=Shenoy%2C+Meetha+V.&rft.au=Sikka%2C+Prateek&rft.date=2023-10-06&rft.pub=IEEE&rft.spage=1&rft.epage=6&rft_id=info:doi/10.1109%2FGCAT59970.2023.10353312&rft.externalDocID=10353312 |