Pandey, J., Asati, A. R., Shenoy, M. V., & Sikka, P. (2023, October 6). Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation. 2023 4th IEEE Global Conference for Advancement in Technology (GCAT), 1-6. https://doi.org/10.1109/GCAT59970.2023.10353312
Citácia podle Chicago (17th ed.)Pandey, Jyoti, Abhijit R. Asati, Meetha V. Shenoy, a Prateek Sikka. "Verification of Hardware Resource Utilization Through High Level Synthesis for FPGA Implementation." 2023 4th IEEE Global Conference for Advancement in Technology (GCAT) 6 Oct. 2023: 1-6. https://doi.org/10.1109/GCAT59970.2023.10353312.
Citácia podľa MLA (8th ed.)Pandey, Jyoti, et al. "Verification of Hardware Resource Utilization Through High Level Synthesis for FPGA Implementation." 2023 4th IEEE Global Conference for Advancement in Technology (GCAT), 6 Oct. 2023, pp. 1-6, https://doi.org/10.1109/GCAT59970.2023.10353312.