Implementation of the Object Detection Algorithm (YOLOV3) on FPGA

From past to present, traffic has always been an important problem in society. Loss of life and material losses due to traffic accidents are quite high. The vast majority of these accidents are closely related to people who drive incorrectly and unconsciously. Therefore, researchers propose various...

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Vydáno v:2021 Innovations in Intelligent Systems and Applications Conference (ASYU) s. 1 - 6
Hlavní autoři: Esen, Fahri, Degirmenci, Ali, Karal, Omer
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 06.10.2021
Témata:
convolutional neural network
Convolutional neural networks
deep learning
deep learning processing unit (DPU)
field programmable gate arrays (FPGA)
Graphics processing units
Logic gates
Object detection
Parallel processing
Real-time systems
Technological innovation
you only look once version 3 (YOLOV3)
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Shrnutí:From past to present, traffic has always been an important problem in society. Loss of life and material losses due to traffic accidents are quite high. The vast majority of these accidents are closely related to people who drive incorrectly and unconsciously. Therefore, researchers propose various methods to solve this problem. Recently, deep learning-based models have been widely used for this purpose. However, these models such as single shot detection (SSD), regions convolutional neural network (R-CNN) and fast regions convolutional neural network (Fast R-CNN) cannot perform real-time object recognition. Because, image processing time (speed) is too long. In this study, the you only look once version 3 (YOLOV3) model, which is one of the deep learning applications, is introduced in real-time to track cars in traffic. YOLOV3 can track objects in real-time. However, the hardware required for the model to give better and faster results is not sufficient today. For this reason, ZCU102 field programmable gate arrays (FPGA) card is used. It has been observed that faster and more accurate results are obtained with the YOLOV3 model run on the FPGA card.
DOI:10.1109/ASYU52992.2021.9599073