A High-Speed Parallel Decoding Algorithm for Erasure Codes in the Distributed Storage System

A high-speed parallel decoding algorithm for erasure codes in the distributed storage system is proposed in this paper. Although erasure codes can tolerate multiple failures, single failures represent 99.75% of recoveries. So the decoding is optimized in only 1 failure first and then complex odd and...

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Veröffentlicht in:2021 2nd Information Communication Technologies Conference (ICTC) S. 283 - 287
Hauptverfasser: Wu, Ruizhen, Wu, Yan, Wang, Mingming, Wang, Lin
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 07.05.2021
Schlagworte:
Cauchy matrix
Communications technology
Decoding
erasure code
gaussian elimination
Hardware design languages
LU factorization Elimination
Vandermonde matrix
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Zusammenfassung:A high-speed parallel decoding algorithm for erasure codes in the distributed storage system is proposed in this paper. Although erasure codes can tolerate multiple failures, single failures represent 99.75% of recoveries. So the decoding is optimized in only 1 failure first and then complex odd and even failure number situations to work with the same module but different parameters and operation flow. The algorithm is implemented in Verilog and synthesized with GF 12nm technology lib. In comparison to Gaussian elimination, LU factorization Elimination the proposed algorithm can have 55.7% to 67% speed reduction clearly have advantages.
DOI:10.1109/ICTC51749.2021.9441660