Spatial-Temporal Transformation of Matrix and Multilayer Algorithms of Binary Number Multiplication

The paper conducted analysis of matrix and multilayer structures of algorithms for multiplication of binary numbers and determined their advantages and disadvantages. The hardware and time characteristics of matrix and multilayer binary number multipliers with the use of improved structures of singl...

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Published in:2019 10th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS) Vol. 2; pp. 691 - 694
Main Authors: Gryga, Volodymyr, Kogut, Igor, Holota, Victor, Kochan, Roman, Rajba, Stanislaw, Gancarczyk, Tomasz, Iatsykovska, Uliana
Format: Conference Proceeding
Language:English
Published: IEEE 01.09.2019
Subjects:
Adders
algorithm
Complexity theory
Convergence
Crystals
Data acquisition
Field programmable gate arrays
flow and spatiak-temporal graph
FPGA
Hardware
matrix and multilayer multiplier
multistep multiplier
Nonhomogeneous media
Periodic structures
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Abstract The paper conducted analysis of matrix and multilayer structures of algorithms for multiplication of binary numbers and determined their advantages and disadvantages. The hardware and time characteristics of matrix and multilayer binary number multipliers with the use of improved structures of single-digit full and half adders are investigated. Using theory of spatio-temporal graphs recursive multistep structures of the multipliers are developed. The analytical expressions for evaluation of the complexity of developed multiplier structures are obtained. It is determined that the algorithmic and conveyor structures of the multipliers have high speed and require significant hardware complexity, in contrast to the proposed multi-cycle structures that have significantly lower performance, but the hardware complexity and the corresponding occupied area on the crystal are minimal. Synthesis of developed multiplier structures on the Xilinx FPGA is performed and the convergence of theoretical and practical results of researches is shown.
AbstractList The paper conducted analysis of matrix and multilayer structures of algorithms for multiplication of binary numbers and determined their advantages and disadvantages. The hardware and time characteristics of matrix and multilayer binary number multipliers with the use of improved structures of single-digit full and half adders are investigated. Using theory of spatio-temporal graphs recursive multistep structures of the multipliers are developed. The analytical expressions for evaluation of the complexity of developed multiplier structures are obtained. It is determined that the algorithmic and conveyor structures of the multipliers have high speed and require significant hardware complexity, in contrast to the proposed multi-cycle structures that have significantly lower performance, but the hardware complexity and the corresponding occupied area on the crystal are minimal. Synthesis of developed multiplier structures on the Xilinx FPGA is performed and the convergence of theoretical and practical results of researches is shown.
Author Holota, Victor
Rajba, Stanislaw
Iatsykovska, Uliana
Kochan, Roman
Gancarczyk, Tomasz
Gryga, Volodymyr
Kogut, Igor
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  givenname: Volodymyr
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  givenname: Igor
  surname: Kogut
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  organization: Vasyl Stefanyk Precarpathian National University,Ivano-Frankivsk,Ukraine
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  givenname: Roman
  surname: Kochan
  fullname: Kochan, Roman
  organization: University of Bielsko-Biala,Bielsko-Biala,Poland,43-309
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  givenname: Stanislaw
  surname: Rajba
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  givenname: Tomasz
  surname: Gancarczyk
  fullname: Gancarczyk, Tomasz
  organization: University of Bielsko-Biala,Bielsko-Biala,Poland,43-309
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  givenname: Uliana
  surname: Iatsykovska
  fullname: Iatsykovska, Uliana
  organization: University of Bielsko-Biala,Bielsko-Biala,Poland,43-309
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Snippet The paper conducted analysis of matrix and multilayer structures of algorithms for multiplication of binary numbers and determined their advantages and...
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StartPage 691
SubjectTerms Adders
algorithm
Complexity theory
Convergence
Crystals
Data acquisition
Field programmable gate arrays
flow and spatiak-temporal graph
FPGA
Hardware
matrix and multilayer multiplier
multistep multiplier
Nonhomogeneous media
Periodic structures
Title Spatial-Temporal Transformation of Matrix and Multilayer Algorithms of Binary Number Multiplication
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