Design of a Fast Chase Algorithm based High Speed Turbo Product Code Decoder

In this paper a high speed turbo product code (TPC) decoder based on fast Chase algorithm is proposed. The improvement in speed is achieved by exploiting the parallelism in the decoder design. A fully parallel soft-in soft-out (SISO) module based on low complexity fast Chase algorithm is designed. T...

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Vydáno v:2021 International Conference on Advances in Computing and Communications (ICACC) s. 1 - 5
Hlavní autoři: Kishore, J. Hari, Yamuna, B., Balasubramanian, Karthi
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 21.10.2021
Témata:
Adders
Chase algorithm
Complexity theory
Costs
Decoder
Decoding
Fast Chase algorithm
Hardware design languages
High speed decoder
Parallel processing
Product codes
Turbo product decoder
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Shrnutí:In this paper a high speed turbo product code (TPC) decoder based on fast Chase algorithm is proposed. The improvement in speed is achieved by exploiting the parallelism in the decoder design. A fully parallel soft-in soft-out (SISO) module based on low complexity fast Chase algorithm is designed. The designed parallel SISO module is used to construct the turbo product decoder using sub block parallelism without any interleaving resources. With this design, a 15 times increase in speed is achieved with a (31,26)^{2} Hamming TPC when compared to that of the decoder that uses sequential SISO module with barrel shifter as interleaving resource. However there is a marginal increase in the area utilized. It is envisaged that, with the use of area efficient adders and comparators, the speed-area trade-off can be mitigated.
DOI:10.1109/ICACC-202152719.2021.9708201