A Comparative Analysis at Binary Arithmetic Coders on FPGA System

In FPGAs system, memory is one of the major limiting factor for processing large data. Meanwhile, FPGAs have bounded on-chip memory, therefore it requires efficient usage of resources in order handle system fault like as power constraints, size and on-demand performance. There are several techniques...

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Vydáno v:2020 International Conference on Industry 4.0 Technology (I4Tech) s. 136 - 140
Hlavní autoři: Sadhana, Choudhary, Raga, Sarika
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.02.2020
Témata:
Adaptation models
Adaptive binary range coder (ABRC)
Channel coding
Context modeling
Context-adaptive binary arithmetic coding (CABAC)
Fault
Field programmable gate arrays
FPGA
Image coding
Transform coding
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Shrnutí:In FPGAs system, memory is one of the major limiting factor for processing large data. Meanwhile, FPGAs have bounded on-chip memory, therefore it requires efficient usage of resources in order handle system fault like as power constraints, size and on-demand performance. There are several techniques of on-chip data compression has been studied and considered by the researchers, and it will keep going to develop. Minimization of power consumption and resource usage, contributes towards the recognition of powerefficient high-level data processing on FPGAs. In this paper, our main intension is to show the effectiveness of ABRC in terms of FPGA implementation aspects. ABRC do not utilize any look up-table which allows reduction in entropy encoder of the memory consumption and provide normal mechanism in order to handle trade-off between precision of probability approximation and the speed of probability adaption. In the result analysis section, we provided the comparison with the existing techniques of coding such as JPEG, MQ-coder (i.e., JPEG2000 standard) and etc. on Xilinx FPGA, the considered ABRC architecture provides reduced memory, consumes less power and comparable operating frequency.
DOI:10.1109/I4Tech48345.2020.9102687