RISC-V Based Secure Processor Architecture for Return Address Protection

RISC-V-based cores are increasingly becoming pop-ular in embedded system applications because of their open-source architecture. Protecting such systems against memory-based attacks is one of the most difficult challenge. Buffer over-flow (BFO) attacks, specifically on Stack, can alter the program e...

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Vydané v:	VLSI design s. 481 - 486
Hlavní autori:	Sharma, Lalit, Goel, Neeraj
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 04.01.2025
Predmet:	Benchmark testing Buffer Overflow Control Flow Integrity Delays Embedded systems Memory management Microarchitecture Out of order Protection Return Address Stack Return-Oriented Programming RISC-V Security Software Very large scale integration
ISSN:	2380-6923
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