Sharma, L., & Goel, N. (2025, January 4). RISC-V Based Secure Processor Architecture for Return Address Protection. VLSI design, 481-486. https://doi.org/10.1109/VLSID64188.2025.00095
Citace podle Chicago (17th ed.)Sharma, Lalit, a Neeraj Goel. "RISC-V Based Secure Processor Architecture for Return Address Protection." VLSI Design 4 Jan. 2025: 481-486. https://doi.org/10.1109/VLSID64188.2025.00095.
Citace podle MLA (9th ed.)Sharma, Lalit, a Neeraj Goel. "RISC-V Based Secure Processor Architecture for Return Address Protection." VLSI Design, 4 Jan. 2025, pp. 481-486, https://doi.org/10.1109/VLSID64188.2025.00095.
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