High-Speed Adaptive Turbo Decoding Algorithm and Its Implementation

In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/Q...

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Bibliographic Details
Published in:Proceedings of 2006 IEEE Information Theory Workshop (ITW '06) : October 22-26, Chengdu, China pp. 104 - 108
Main Authors: Min Hyuk Kim, Jin-Hee Jeong, Ji-Won Jung
Format: Conference Proceeding
Language:English
Published: IEEE 01.10.2006
Subjects:
Channel coding
Delay
Design engineering
Energy consumption
Field programmable gate arrays
Hardware
Iterative decoding
Modulation coding
Quadrature phase shift keying
Turbo codes
ISBN:9781424400676, 1424400678
Online Access:Get full text
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Summary:In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. .The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder
ISBN:9781424400676
1424400678
DOI:10.1109/ITW2.2006.323766