High performance and low complexity Max-Log-MAP algorithm for FPGA turbo decoder

In this paper, we focus on implementing turbo decoder compliant with 3GPP spec, we adopted sliding window method with forward state metric as an accuracy initialization value and a modified Max-Log-MAP algorithm which modify extrinsic information by a scaling factor R. Then, we can implement the who...

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Vydané v:	The 7th International Conference on Advanced Communication Technology, 2005, ICACT 2005 Ročník 2; s. 833 - 838
Hlavní autori:	Mao-Hsiu Hsu, Jhin-Fang Huang
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 2005
Predmet:	Cost function Delay Field programmable gate arrays Hardware Iterative algorithms Iterative decoding Logic gates Noise generators Throughput Turbo codes
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