Fast, minimal decoding complexity, system level, binary systematic (41, 32) single-error-correcting codes for on-chip DRAM applications - Amir, K.; Eric, B. (Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001)
Fast, minimal decoding complexity, system level, binary systematic (41, 32) single-error-correcting codes for on-chip DRAM applications are presented. These (41, 32) codes allow fast single error correcting with three parity bit penalty and can be used in combinational circuits with minimal (ultimate) decoding complexity.