Fixed-outline floorplanning through better local search

We study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SOCs. We empirically show that the fixed-outline floorplan problem instances are significantly harder than the well-researched instances without fixed outline...

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Bibliographic Details

Published in:	Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001 pp. 328 - 334
Main Authors:	Adya, S.N., Markov, I.L.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 2001
Subjects:	Application specific integrated circuits Computational modeling Context modeling Modems Pins Routing Shape Simulated annealing
ISBN:	9780769512006, 0769512003
ISSN:	1063-6404
Online Access:	Get full text
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