Fixed-outline floorplanning through better local search

We study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SOCs. We empirically show that the fixed-outline floorplan problem instances are significantly harder than the well-researched instances without fixed outline...

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Vydáno v:Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001 s. 328 - 334
Hlavní autoři: Adya, S.N., Markov, I.L.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 2001
Témata:
Application specific integrated circuits
Computational modeling
Context modeling
Modems
Pins
Routing
Shape
Simulated annealing
ISBN:9780769512006, 0769512003
ISSN:1063-6404
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Shrnutí:We study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SOCs. We empirically show that the fixed-outline floorplan problem instances are significantly harder than the well-researched instances without fixed outline. Furthermore, we suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context. Our empirical evaluation is based on a new floorplanner implementation Parquet-1 that can operate in both outline free and fixed-outline modes. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported. A similar slack computation is possible with many other floorplan representations. In all cases, the slowdown is by a constant factor - roughly 2x.
ISBN:9780769512006
0769512003
ISSN:1063-6404
DOI:10.1109/ICCD.2001.955047