A hardware efficient parallel Viterbi algorithm

A hardware efficient block processing scheme is proposed for concurrent implementation of the Viterbi algorithm. The throughput increase is proportional to the increase in hardware complexity at the expense of latency. Advantages of the algorithm over other parallel schemes are that the reduction of...

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Bibliographic Details

Published in:	Proceedings of the ... IEEE International Conference on Acoustics, Speech and Signal Processing (1998) pp. 893 - 896 vol.2
Main Authors:	Black, P.J., Meng, T.H.-Y.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 1990
Subjects:	Data mining Decoding Delay Hardware Information rates Intersymbol interference Throughput Transmitters Viterbi algorithm
ISSN:	1520-6149
Online Access:	Get full text
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