A hardware efficient parallel Viterbi algorithm
A hardware efficient block processing scheme is proposed for concurrent implementation of the Viterbi algorithm. The throughput increase is proportional to the increase in hardware complexity at the expense of latency. Advantages of the algorithm over other parallel schemes are that the reduction of...
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| Published in: | Proceedings of the ... IEEE International Conference on Acoustics, Speech and Signal Processing (1998) pp. 893 - 896 vol.2 |
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| Main Authors: | , |
| Format: | Conference Proceeding |
| Language: | English |
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IEEE
1990
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| ISSN: | 1520-6149 |
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| Abstract | A hardware efficient block processing scheme is proposed for concurrent implementation of the Viterbi algorithm. The throughput increase is proportional to the increase in hardware complexity at the expense of latency. Advantages of the algorithm over other parallel schemes are that the reduction of the information rate due to bit stuffing at the transmitter and extraction of block synchronization from the received data are not necessary. The scheme is well suited to the problem of sequence estimation in the presence of intersymbol interference, although it can be applied to any decoder based on the Viterbi algorithm.< > |
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| AbstractList | A hardware efficient block processing scheme is proposed for concurrent implementation of the Viterbi algorithm. The throughput increase is proportional to the increase in hardware complexity at the expense of latency. Advantages of the algorithm over other parallel schemes are that the reduction of the information rate due to bit stuffing at the transmitter and extraction of block synchronization from the received data are not necessary. The scheme is well suited to the problem of sequence estimation in the presence of intersymbol interference, although it can be applied to any decoder based on the Viterbi algorithm.< > |
| Author | Black, P.J. Meng, T.H.-Y. |
| Author_xml | – sequence: 1 givenname: P.J. surname: Black fullname: Black, P.J. organization: Inf. Syst. Lab., Stanford Univ., CA, USA – sequence: 2 givenname: T.H.-Y. surname: Meng fullname: Meng, T.H.-Y. organization: Inf. Syst. Lab., Stanford Univ., CA, USA |
| BookMark | eNotj81qAjEURrOwULV9AVd5gdF7zZ38LEX6B0ILtt1KMnNTU-IomYHSt69FVwfO4nx8EzHqjh0LMUOYI4JbvKxX2-3bHJ37F7WzZiTGWC-h0kjuVkz6_hsArCE7FouV3PvS_vjCkmNMTeJukCdffM6c5WcauIQkff46ljTsD3fiJvrc8_2VU_Hx-PC-fq42r0_n4U2VEGiovGlVg7FpNCh2tLREpBQow3UMsTVMGlvN1iqFLlDtyegQANETqrNQUzG7dBMz704lHXz53V3uqD9OB0HS |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IL CBEJK RIE RIL |
| DOI | 10.1109/ICASSP.1990.115987 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP All) 1998-Present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EndPage | 896 vol.2 |
| ExternalDocumentID | 115987 |
| GroupedDBID | 23M 29P 6IE 6IF 6IH 6IK 6IL 6IM 6IN AAJGR AAWTH ABLEC ACGFS ADZIZ ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO IEGSK IJVOP IPLJI M43 OCL RIE RIL RNS |
| ID | FETCH-LOGICAL-i104t-a7d3c1fcc603e942844433037e5fbfd7e461d6e883319b45a476bb011a4139b43 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 0 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=115987&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 1520-6149 |
| IngestDate | Tue Aug 26 17:00:25 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-i104t-a7d3c1fcc603e942844433037e5fbfd7e461d6e883319b45a476bb011a4139b43 |
| ParticipantIDs | ieee_primary_115987 |
| PublicationCentury | 1900 |
| PublicationDate | 19900000 |
| PublicationDateYYYYMMDD | 1990-01-01 |
| PublicationDate_xml | – year: 1990 text: 19900000 |
| PublicationDecade | 1990 |
| PublicationTitle | Proceedings of the ... IEEE International Conference on Acoustics, Speech and Signal Processing (1998) |
| PublicationTitleAbbrev | ICASSP |
| PublicationYear | 1990 |
| Publisher | IEEE |
| Publisher_xml | – name: IEEE |
| SSID | ssj0008748 |
| Score | 1.2883539 |
| Snippet | A hardware efficient block processing scheme is proposed for concurrent implementation of the Viterbi algorithm. The throughput increase is proportional to the... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 893 |
| SubjectTerms | Data mining Decoding Delay Hardware Information rates Intersymbol interference Throughput Transmitters Viterbi algorithm |
| Title | A hardware efficient parallel Viterbi algorithm |
| URI | https://ieeexplore.ieee.org/document/115987 |
| WOSCitedRecordID | wos115987&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3PS8MwFA5ueNCLOif-Jgevce2aJs1xDIeCjMF07DbS5kULdZXa6b9vXjqnghdv4R1CftB-70vyfY-QK4UwaAPD-jbijBthmA7ijClkzNoKnfgb3dm9HI-T-VxN1j7bXgsDAP7xGVxj09_lmzJb4VFZz2UvjiK3SEtK0Ui1Nj_dRPpCWQ6NkA1x9aWPCVTvbjiYTicoy8MA9vCrkooHktHev4awT7rfgjw62UDNAdmCZYfs_vASPCS9AUUB1YeugIL3hXAdUXT2Lgoo6AylxmlOdfFUVnn9_NIlj6Obh-EtW1dDYLmjTDXT0kRZaLNMBBEoxxo455EDIAmxTa2RwEVoBGDx4FClPNZcijR1n692OOUC0RFpL8slHBMKLgsQLnWyobVcicTtY9xXEIPgkKT96IR0cOaL18bwYtFM-vTP6BnZwZVtTiXOSbuuVnBBtrP3On-rLv0mfQIoAJAU |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1dT8IwFL1RNFFfVMT47R58reyj69ZHQiQQkZCAhDfSrbe6ZIKZQ_--bYeoiS--Nfeh6Ue2c0_bcy7ADTcwqFxJfBVQQiWTRLhhSrhhzEIxEdsb3Uk_Ggzi6ZQPVz7bVguDiPbxGd6apr3Ll4t0aY7Kmjp70RR5E7ZCSn23Emutf7txZEtlaTwyfIjyL4WMy5u9dms0GhphngmYPn7VUrFQ0tn_1yAOoPEtyXOGa7A5hA2c12Hvh5vgETRbjpFQfYgCHbTOELojx3h75znmzsSIjZPMEfnTosjK55cGPHbuxu0uWdVDIJkmTSURkQxST6UpcwPkmjdQSgMNQRGGKlEyQso8ydCUD_Z4QkNBI5Yk-gMWGql0IDiG2nwxxxNwUOcBTCdPylOKchbrnQx9jiEyinHiB6dQNzOfvVaWF7Nq0md_Rq9hpzt-6M_6vcH9OeyaVa7OKC6gVhZLvITt9L3M3ooru2Gf2xaTWw |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=proceeding&rft.title=Proceedings+of+the+...+IEEE+International+Conference+on+Acoustics%2C+Speech+and+Signal+Processing+%281998%29&rft.atitle=A+hardware+efficient+parallel+Viterbi+algorithm&rft.au=Black%2C+P.J.&rft.au=Meng%2C+T.H.-Y.&rft.date=1990-01-01&rft.pub=IEEE&rft.issn=1520-6149&rft.spage=893&rft.epage=896+vol.2&rft_id=info:doi/10.1109%2FICASSP.1990.115987&rft.externalDocID=115987 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1520-6149&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1520-6149&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1520-6149&client=summon |