Pausible clocking: a first step toward heterogeneous systems

This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous modules operating independently. In this scheme, communication between every pair of modules is done through an asynchronous FIFO channel; communication between...

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Vydáno v:Proceedings International Conference on Computer Design. VLSI in Computers and Processors s. 118 - 123
Hlavní autoři: Yun, K.Y., Donohue, R.P.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 1996
Témata:
Circuits
Clocks
Communication system control
Delay
Drives
Frequency synchronization
Latches
System-on-a-chip
Testing
Time factors
ISBN:0818675543, 9780818675546
ISSN:1063-6404
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Shrnutí:This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous modules operating independently. In this scheme, communication between every pair of modules is done through an asynchronous FIFO channel; communication between a module and the FIFO is done using a request/acknowledge handshaking. Synchronization of handshaking signals to the local module clock is done in an unconventional way-the local clock built out of a ring oscillator is paused or stretched, if necessary, to ensure that the handshaking signal satisfies setup and hold time constraints with respect to the local clock. We constructed a test bed consisting of two synchronous modules with pausible clocking control and an asynchronous FIFO on a MOSIS 1.2 /spl mu/m CMOS chip. The resulting system functions reliably up to the local clock frequency of 220 MHz (according to SPICE simulation)-the maximum clock rate is limited by the ring oscillator not the pausible clocking control. Preliminary test results indicate that the fabricated chips operate correctly as simulated.
ISBN:0818675543
9780818675546
ISSN:1063-6404
DOI:10.1109/ICCD.1996.563543