Pausible clocking: a first step toward heterogeneous systems

This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous modules operating independently. In this scheme, communication between every pair of modules is done through an asynchronous FIFO channel; communication between...

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Bibliographic Details

Published in:	Proceedings International Conference on Computer Design. VLSI in Computers and Processors pp. 118 - 123
Main Authors:	Yun, K.Y., Donohue, R.P.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 1996
Subjects:	Circuits Clocks Communication system control Delay Drives Frequency synchronization Latches System-on-a-chip Testing Time factors
ISBN:	0818675543, 9780818675546
ISSN:	1063-6404
Online Access:	Get full text
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